So, firstly I would like to tell You something about DDS. What it is?
DDS - Direct Digital Synthesizer is a technique to create different waveform. In fact, this allow us to generate signal with adjustable frequency. Signal on output is determined by clock frequency and array with data. In essence, the reference clock frequency is “divided down” in a DDS
architecture by the scaling factor set forth in a programmable binary tuning word.
Main adventages of DDS:
- resolution of output signal can be decreased to micro-Hz.
- DDS allow to avoid some problems connected with (i.e.) temperatur which appear in analog system.
- better frequency control than in other systems.
... and nothing about drawbacks ;) but there are ...
Figure 1. Simple Direct Digital Synthesizer
Principle of operation is simply to understand. We have array with sample of sin (one period) in memory. In this case reference osc is a timer. Timer is utilizing to generate interrupt. In this interrupt (on output of DAC) is setting value of next sample from array, where size of steps(jump) is equal to M. This value defined frequency of signal.
Figure 2. Digital Phase Wheel
As You can see fo is dependent only on M, bacouse fc and N is always the same (fc is frequency of timer interrupt and N is a amount of bits each variable in array with data. So, fc/2^n is resolution of output signal. It's very important issue.
I have written above, that output signal is changing in each timer interrupt. So, this leads to phenomena which is shown below:
Figure 3. Output signal with/(out) filter.
You can see, that set value on DAC output is keeping by certain time and our signal looks like stairs. To mitigate signal we should use DP filter (red line on picture).
So, this is all for today. Next post will come soon!
nice job
OdpowiedzUsuńIt is really nice explanation, im waiting for code :D
OdpowiedzUsuńwow...your project is very interesting.I'm going to start my project which will be based on your theory :).
OdpowiedzUsuńTen komentarz został usunięty przez autora.
OdpowiedzUsuńHi!
OdpowiedzUsuńThis is very interesting project! Firstly I'd like to mention that some parts of your theory have been described incorrectly. Mainly, the system output frequency depend on: sampling interval (this is correct - you denoted this as frequency of timer interrupt), tunning word M (which is also correct), and amount of bits that each variable (constants saved in memory rather then variables) consists of. This last statement is incorrect, because the number of bits of constants (size of each sample) is only related to your DAC resolution. So, what is the correct anwser?
Describing the basic DDS system we know that it has some components such as: Frequency Control Register (M - do not look at label M in Figure 1, this is related to sth different), Numerically-Controlled Oscillator (NCO), DAC and Low Pass Filter. When the first two modules work on the N-bit wide registers, and the memory is addressed using the same amount of bits, then the output frequency of the system is related to N. In this case size of LUT (lookup table) is described by 2^N samples, and each sample is composed of L bits (resolution of used DAC).
Architecture that I described above has many drawbacks. One and the most important is that, the LUT has to be very large when we want to generate signals in relevant range of frequency. For example if N is equel to 12, the size of LUT is 2^12 = 4096. If Fs (sampling freq.) = 1MHz, then the resolutin of DDS system is equel to fs/4096 = 244.14 Hz (this is also min. output frequency). We can calculate max. output freq. using assumption: 30% * fs/2 = 150kHz (this can be achived only with well designed LPF).
Sometimes we want to generate faster signals and achive better resolutions. This can be done by making some addressing word truncation. Now we don't use all N bits of Phase Register to address LUT table, but only some MSBs. This phase truncation puts some distortions in the signal. This distortions can be visualized as spurs is frequency domain. But do not worry! In the most cases this spurs has small energy comparing to the carrier. Difference between carrier level and max. spurs level is called Spurious-Free Dynamic Range. This range has to be greater then 40dB (it's my suggestion)! Value of SFDR can be calculated, but this is not the place to describe it. I can tell you as a hint that SFDR is related to the number of DAC bits and the number of truncated bits in phase register.
The biggest adventage of truncation of phase register (word that directly address LUT table) is that, the LUT table can be smaller to achive the same or better output frequency range (leaving the frequency resolutin on the same level)! The oputput frequency is then described by equation: f_out = M*fs/2^N, where M is value of frequency reg. (somethimes called increment reg.), fs is sampling freq. and N is the size (number of bits) of Phase Register (without truncatin)!!! Please do not mix up the M from Figure 1 with M in the last sentence!
You don't describe what exactly is showen in the Figure 1. This is also important to understand why the amplitude of the output signal will be dropping (on the output of the LPF) with increasing the frequency. This is due to ... ;) This is your job ;)
At the end I'd like to thank you for your project! It's very nice and I'm looking forward for your next posts! ;)
K^2 !!