The signal generator is still under construction.

Hello.
In previous post I described theory of DDS - now I am going to deal with all connected with construction:
- power,
- communication with PC,
- PCB board,
- etc...

As I wrote in first post, signal generator will be independent device controlled by PC. In last week I created electrical schematic for power and STM32F100. Signal generator will be powered by battery Li-po 3.7V and charged from USB - I will use charger from TI.

Next important issue is communication between PC and SG (signal generator). Communication will be based on modules HMTRP which working on 868MHz. There are modules simply to utilize and enough to my use.

I hope that in next post I will be able to show you picture with results of my work.

Theory! Principle operation of DDS.

It is high time to explain, how my generator will be acted.
So, firstly I would like to tell You something about DDS. What it is?

DDS - Direct Digital Synthesizer is a technique to create different waveform. In fact, this allow  us to generate signal with adjustable frequency. Signal on output is determined by clock frequency and array with data. In essence, the reference clock frequency is “divided down” in a DDS
architecture by the scaling factor set forth in a programmable binary tuning word.
Main adventages of DDS:
- resolution of output signal can be decreased to micro-Hz.
- DDS allow to avoid some problems connected with (i.e.) temperatur which appear in analog     system. 
- better frequency control than in other systems.

... and nothing about drawbacks ;) but there are ...

 Figure 1. Simple Direct Digital Synthesizer

Principle of operation is simply to understand. We have array with sample of sin (one period) in memory. In this case reference osc is a timer. Timer is utilizing to generate interrupt. In this interrupt (on output of DAC) is setting value of next sample from array, where size of steps(jump)  is equal to M. This value defined frequency of signal. 

Figure 2. Digital Phase Wheel

As You can see fo is dependent only on M, bacouse fc and N is always the same (fc is frequency of timer interrupt and N is  a amount of bits each variable in array with data. So, fc/2^n is resolution of output signal. It's very important issue.

I have written above, that output signal is changing in each timer interrupt. So, this leads to phenomena which is shown below:

 

Figure 3. Output signal with/(out) filter.

You can see, that set value on DAC output is keeping by certain time and our signal looks like stairs. To mitigate signal we should use DP filter (red line on picture).

So, this is all for today. Next post will come soon!